web/test/unittest_urlrewrite.py
author Sylvain Thénault <sylvain.thenault@logilab.fr>
Thu, 26 Aug 2010 11:35:02 +0200
branchstable
changeset 6160 12038ca95f0f
parent 5424 8ecbcbff9777
child 6340 470d8e828fda
permissions -rw-r--r--
Added tag cubicweb-version-3.9.5 for changeset 0a1fce8ddc67
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
5421
8167de96c523 proper licensing information (LGPL-2.1). Hope I get it right this time.
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents: 4715
diff changeset
     1
# copyright 2003-2010 LOGILAB S.A. (Paris, FRANCE), all rights reserved.
8167de96c523 proper licensing information (LGPL-2.1). Hope I get it right this time.
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents: 4715
diff changeset
     2
# contact http://www.logilab.fr/ -- mailto:contact@logilab.fr
8167de96c523 proper licensing information (LGPL-2.1). Hope I get it right this time.
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents: 4715
diff changeset
     3
#
8167de96c523 proper licensing information (LGPL-2.1). Hope I get it right this time.
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents: 4715
diff changeset
     4
# This file is part of CubicWeb.
8167de96c523 proper licensing information (LGPL-2.1). Hope I get it right this time.
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents: 4715
diff changeset
     5
#
8167de96c523 proper licensing information (LGPL-2.1). Hope I get it right this time.
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents: 4715
diff changeset
     6
# CubicWeb is free software: you can redistribute it and/or modify it under the
8167de96c523 proper licensing information (LGPL-2.1). Hope I get it right this time.
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents: 4715
diff changeset
     7
# terms of the GNU Lesser General Public License as published by the Free
8167de96c523 proper licensing information (LGPL-2.1). Hope I get it right this time.
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents: 4715
diff changeset
     8
# Software Foundation, either version 2.1 of the License, or (at your option)
8167de96c523 proper licensing information (LGPL-2.1). Hope I get it right this time.
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents: 4715
diff changeset
     9
# any later version.
8167de96c523 proper licensing information (LGPL-2.1). Hope I get it right this time.
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents: 4715
diff changeset
    10
#
5424
8ecbcbff9777 replace logilab-common by CubicWeb in disclaimer
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents: 5421
diff changeset
    11
# CubicWeb is distributed in the hope that it will be useful, but WITHOUT
5421
8167de96c523 proper licensing information (LGPL-2.1). Hope I get it right this time.
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents: 4715
diff changeset
    12
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
8167de96c523 proper licensing information (LGPL-2.1). Hope I get it right this time.
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents: 4715
diff changeset
    13
# FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public License for more
8167de96c523 proper licensing information (LGPL-2.1). Hope I get it right this time.
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents: 4715
diff changeset
    14
# details.
8167de96c523 proper licensing information (LGPL-2.1). Hope I get it right this time.
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents: 4715
diff changeset
    15
#
8167de96c523 proper licensing information (LGPL-2.1). Hope I get it right this time.
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents: 4715
diff changeset
    16
# You should have received a copy of the GNU Lesser General Public License along
8167de96c523 proper licensing information (LGPL-2.1). Hope I get it right this time.
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents: 4715
diff changeset
    17
# with CubicWeb.  If not, see <http://www.gnu.org/licenses/>.
1977
606923dff11b big bunch of copyright / docstring update
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents: 1900
diff changeset
    18
"""
606923dff11b big bunch of copyright / docstring update
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents: 1900
diff changeset
    19
606923dff11b big bunch of copyright / docstring update
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents: 1900
diff changeset
    20
"""
0
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    21
from logilab.common.testlib import TestCase, unittest_main
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    22
2773
b2530e3e0afb [testlib] #345052 and #344207: major test lib refactoring/cleanup + update usage
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents: 2439
diff changeset
    23
from cubicweb.devtools.testlib import CubicWebTC
b2530e3e0afb [testlib] #345052 and #344207: major test lib refactoring/cleanup + update usage
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents: 2439
diff changeset
    24
from cubicweb.devtools.fake import FakeRequest
0
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    25
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    26
from cubicweb.web.views.urlrewrite import SimpleReqRewriter, SchemaBasedRewriter, rgx, rgx_action
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    27
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    28
3465
01616e5fa590 [tests] make unittest_urlrewrite pass again
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents: 3185
diff changeset
    29
class UrlRewriteTC(CubicWebTC):
0
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    30
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    31
    def test_auto_extend_rules(self):
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    32
        class Rewriter(SimpleReqRewriter):
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    33
            rules = [
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    34
                ('foo', dict(rql='Foo F')),
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    35
                ('/index', dict(vid='index2')),
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    36
                ]
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    37
        rules = []
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    38
        for pattern, values in Rewriter.rules:
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    39
            if hasattr(pattern, 'pattern'):
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    40
                pattern = pattern.pattern
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    41
            rules.append((pattern, values))
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    42
        self.assertListEquals(rules, [
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    43
            ('foo' , dict(rql='Foo F')),
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    44
            ('/index' , dict(vid='index2')),
2780
ad1dfc3855b0 B web/tests back to green
Nicolas Chauvat <nicolas.chauvat@logilab.fr>
parents: 2439
diff changeset
    45
            ('/_', dict(vid='manage')),
ad1dfc3855b0 B web/tests back to green
Nicolas Chauvat <nicolas.chauvat@logilab.fr>
parents: 2439
diff changeset
    46
            ('/_registry', dict(vid='registry')),
2439
77d8dd77acb3 [cleanup] fix tests
Nicolas Chauvat <nicolas.chauvat@logilab.fr>
parents: 1977
diff changeset
    47
            ('/schema', dict(vid='schema')),
1900
8dd4bb69c73d [tests] fix test after eproperties got renamed to cwproperties
Nicolas Chauvat <nicolas.chauvat@logilab.fr>
parents: 1802
diff changeset
    48
            ('/myprefs', dict(vid='propertiesform')),
8dd4bb69c73d [tests] fix test after eproperties got renamed to cwproperties
Nicolas Chauvat <nicolas.chauvat@logilab.fr>
parents: 1802
diff changeset
    49
            ('/siteconfig', dict(vid='systempropertiesform')),
2439
77d8dd77acb3 [cleanup] fix tests
Nicolas Chauvat <nicolas.chauvat@logilab.fr>
parents: 1977
diff changeset
    50
            ('/siteinfo', dict(vid='info')),
0
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    51
            ('/manage', dict(vid='manage')),
2439
77d8dd77acb3 [cleanup] fix tests
Nicolas Chauvat <nicolas.chauvat@logilab.fr>
parents: 1977
diff changeset
    52
            ('/notfound', dict(vid='404')),
77d8dd77acb3 [cleanup] fix tests
Nicolas Chauvat <nicolas.chauvat@logilab.fr>
parents: 1977
diff changeset
    53
            ('/error', dict(vid='error')),
77d8dd77acb3 [cleanup] fix tests
Nicolas Chauvat <nicolas.chauvat@logilab.fr>
parents: 1977
diff changeset
    54
            ('/sparql', dict(vid='sparql')),
4715
d3f87ee74fe4 [test] fix test broken by arthur processinfo patch
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents: 4390
diff changeset
    55
            ('/processinfo', dict(vid='processinfo')),
4390
0285c1fa1459 test fixes
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents: 4252
diff changeset
    56
            ('/schema/([^/]+?)/?$', {'rql': r'Any X WHERE X is CWEType, X name "\1"', 'vid': 'primary'}),
0
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    57
            ('/add/([^/]+?)/?$' , dict(vid='creation', etype=r'\1')),
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    58
            ('/doc/images/(.+?)/?$', dict(fid='\\1', vid='wdocimages')),
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    59
            ('/doc/?$', dict(fid='main', vid='wdoc')),
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    60
            ('/doc/(.+?)/?$', dict(fid='\\1', vid='wdoc')),
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    61
            ('/changelog/?$', dict(vid='changelog')),
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    62
            # now in SchemaBasedRewriter
1802
d628defebc17 delete-trailing-whitespace + some copyright update
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents: 1398
diff changeset
    63
            #('/search/(.+)$', dict(rql=r'Any X WHERE X has_text "\1"')),
0
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    64
            ])
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    65
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    66
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    67
    def test_no_extend_rules(self):
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    68
        class Rewriter(SimpleReqRewriter):
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    69
            ignore_baseclass_rules = True
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    70
            rules = [
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    71
                ('foo', dict(rql='Foo F')),
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    72
                ('/index', dict(vid='index2')),
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    73
                ]
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    74
        self.assertListEquals(Rewriter.rules, [
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    75
            ('foo' , dict(rql='Foo F')),
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    76
            ('/index' , dict(vid='index2')),
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    77
            ])
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    78
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    79
    def test_basic_transformation(self):
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    80
        """test simple string-based rewrite"""
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    81
        req = FakeRequest()
3465
01616e5fa590 [tests] make unittest_urlrewrite pass again
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents: 3185
diff changeset
    82
        rewriter = SimpleReqRewriter(req)
0
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    83
        self.assertRaises(KeyError, rewriter.rewrite, req, '/view?vid=whatever')
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    84
        self.assertEquals(req.form, {})
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    85
        rewriter.rewrite(req, '/index')
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    86
        self.assertEquals(req.form, {'vid' : "index"})
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    87
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    88
    def test_regexp_transformation(self):
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    89
        """test regexp-based rewrite"""
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    90
        req = FakeRequest()
3465
01616e5fa590 [tests] make unittest_urlrewrite pass again
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents: 3185
diff changeset
    91
        rewriter = SimpleReqRewriter(req)
0
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    92
        rewriter.rewrite(req, '/add/Task')
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    93
        self.assertEquals(req.form, {'vid' : "creation", 'etype' : "Task"})
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    94
        req = FakeRequest()
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    95
        rewriter.rewrite(req, '/add/Task/')
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    96
        self.assertEquals(req.form, {'vid' : "creation", 'etype' : "Task"})
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    97
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    98
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
    99
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
   100
2773
b2530e3e0afb [testlib] #345052 and #344207: major test lib refactoring/cleanup + update usage
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents: 2439
diff changeset
   101
class RgxActionRewriteTC(CubicWebTC):
0
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
   102
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
   103
    def setup_database(self):
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
   104
        self.p1 = self.create_user(u'user1')
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
   105
        self.p1.set_attributes(firstname=u'joe', surname=u'Dalton')
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
   106
        self.p2 = self.create_user(u'user2')
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
   107
        self.p2.set_attributes(firstname=u'jack', surname=u'Dalton')
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
   108
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
   109
    def test_rgx_action_with_transforms(self):
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
   110
        class TestSchemaBasedRewriter(SchemaBasedRewriter):
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
   111
            rules = [
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
   112
                (rgx('/(?P<sn>\w+)/(?P<fn>\w+)'), rgx_action(r'Any X WHERE X surname %(sn)s, X firstname %(fn)s',
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
   113
                                                                             argsgroups=('sn', 'fn'),
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
   114
                                                                             transforms={'sn' : unicode.capitalize,
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
   115
                                                                                         'fn' : unicode.lower,})),
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
   116
                ]
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
   117
        req = self.request()
3465
01616e5fa590 [tests] make unittest_urlrewrite pass again
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents: 3185
diff changeset
   118
        rewriter = TestSchemaBasedRewriter(req)
0
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
   119
        pmid, rset = rewriter.rewrite(req, u'/DaLToN/JoE')
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
   120
        self.assertEquals(len(rset), 1)
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
   121
        self.assertEquals(rset[0][0], self.p1.eid)
1802
d628defebc17 delete-trailing-whitespace + some copyright update
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents: 1398
diff changeset
   122
3168
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   123
    def test_inheritance_precedence(self):
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   124
        RQL1 = 'Any C WHERE C is CWEType'
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   125
        RQL2 = 'Any C WHERE C is CWUser'
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   126
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   127
        class BaseRewriter(SchemaBasedRewriter):
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   128
            rules = [
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   129
               (rgx('/collector(.*)'),
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   130
                rgx_action(rql=RQL1,
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   131
                    form=dict(vid='baseindex')),
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   132
                ),
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   133
                ]
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   134
        class Rewriter(BaseRewriter):
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   135
            rules = [
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   136
               (rgx('/collector/something(/?)'),
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   137
                rgx_action(rql=RQL2,
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   138
                    form=dict(vid='index')),
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   139
                ),
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   140
                ]
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   141
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   142
        req = self.request()
3465
01616e5fa590 [tests] make unittest_urlrewrite pass again
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents: 3185
diff changeset
   143
        rewriter = Rewriter(req)
3168
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   144
        pmid, rset = rewriter.rewrite(req, '/collector')
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   145
        self.assertEquals(rset.rql, RQL1)
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   146
        self.assertEquals(req.form, {'vid' : "baseindex"})
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   147
        pmid, rset = rewriter.rewrite(req, '/collector/something')
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   148
        self.assertEquals(rset.rql, RQL2)
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   149
        self.assertEquals(req.form, {'vid' : "index"})
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   150
        pmid, rset = rewriter.rewrite(req, '/collector/something/')
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   151
        self.assertEquals(req.form, {'vid' : "index"})
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   152
        self.assertEquals(rset.rql, RQL2)
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   153
        pmid, rset = rewriter.rewrite(req, '/collector/somethingelse/')
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   154
        self.assertEquals(rset.rql, RQL1)
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   155
        self.assertEquals(req.form, {'vid' : "baseindex"})
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   156
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   157
    def test_inheritance_precedence_same_rgx(self):
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   158
        RQL1 = 'Any C WHERE C is CWEType'
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   159
        RQL2 = 'Any C WHERE C is CWUser'
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   160
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   161
        class BaseRewriter(SchemaBasedRewriter):
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   162
            rules = [
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   163
               (rgx('/collector(.*)'),
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   164
                rgx_action(rql=RQL1,
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   165
                    form=dict(vid='baseindex')),
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   166
                ),
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   167
                ]
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   168
        class Rewriter(BaseRewriter):
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   169
            rules = [
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   170
               (rgx('/collector(.*)'),
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   171
                rgx_action(rql=RQL2,
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   172
                    form=dict(vid='index')),
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   173
                ),
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   174
                ]
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   175
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   176
        req = self.request()
3465
01616e5fa590 [tests] make unittest_urlrewrite pass again
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents: 3185
diff changeset
   177
        rewriter = Rewriter(req)
3168
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   178
        pmid, rset = rewriter.rewrite(req, '/collector')
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   179
        self.assertEquals(rset.rql, RQL2)
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   180
        self.assertEquals(req.form, {'vid' : "index"})
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   181
        pmid, rset = rewriter.rewrite(req, '/collector/something')
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   182
        self.assertEquals(rset.rql, RQL2)
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   183
        self.assertEquals(req.form, {'vid' : "index"})
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   184
        pmid, rset = rewriter.rewrite(req, '/collector/something/')
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   185
        self.assertEquals(req.form, {'vid' : "index"})
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   186
        self.assertEquals(rset.rql, RQL2)
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   187
        pmid, rset = rewriter.rewrite(req, '/collector/somethingelse/')
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   188
        self.assertEquals(rset.rql, RQL2)
1ecd1b6d6f1b [tests] inheritance_precedence in url rewrite
Julien Jehannet <julien.jehannet@logilab.fr>
parents: 2780
diff changeset
   189
        self.assertEquals(req.form, {'vid' : "index"})
1802
d628defebc17 delete-trailing-whitespace + some copyright update
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents: 1398
diff changeset
   190
0
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
   191
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
   192
if __name__ == '__main__':
b97547f5f1fa Showtime !
Adrien Di Mascio <Adrien.DiMascio@logilab.fr>
parents:
diff changeset
   193
    unittest_main()