| author | Rémi Cardona <remi.cardona@logilab.fr> |
| Mon, 14 Apr 2014 13:31:19 +0200 | |
| branch | stable |
| changeset 9704 | 43c9896d0e9f |
| parent 9695 | aa982b7c3f2a |
| child 9903 | d1fdbdbab194 |
| permissions | -rw-r--r-- |
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9181
2eac0aa1d3f6
[dataimport] ucsvreader should skip empty lines unless specified otherwise. Closes #3035944
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents:
diff
changeset
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1 |
from StringIO import StringIO |
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2eac0aa1d3f6
[dataimport] ucsvreader should skip empty lines unless specified otherwise. Closes #3035944
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents:
diff
changeset
|
2 |
from logilab.common.testlib import TestCase, unittest_main |
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2eac0aa1d3f6
[dataimport] ucsvreader should skip empty lines unless specified otherwise. Closes #3035944
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents:
diff
changeset
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from cubicweb import dataimport |
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9695
aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
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5 |
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2eac0aa1d3f6
[dataimport] ucsvreader should skip empty lines unless specified otherwise. Closes #3035944
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents:
diff
changeset
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class UcsvreaderTC(TestCase): |
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2eac0aa1d3f6
[dataimport] ucsvreader should skip empty lines unless specified otherwise. Closes #3035944
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents:
diff
changeset
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7 |
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2eac0aa1d3f6
[dataimport] ucsvreader should skip empty lines unless specified otherwise. Closes #3035944
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents:
diff
changeset
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8 |
def test_empty_lines_skipped(self): |
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2eac0aa1d3f6
[dataimport] ucsvreader should skip empty lines unless specified otherwise. Closes #3035944
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents:
diff
changeset
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stream = StringIO('''a,b,c,d, |
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2eac0aa1d3f6
[dataimport] ucsvreader should skip empty lines unless specified otherwise. Closes #3035944
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents:
diff
changeset
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1,2,3,4, |
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2eac0aa1d3f6
[dataimport] ucsvreader should skip empty lines unless specified otherwise. Closes #3035944
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents:
diff
changeset
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,,,, |
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2eac0aa1d3f6
[dataimport] ucsvreader should skip empty lines unless specified otherwise. Closes #3035944
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents:
diff
changeset
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,,,, |
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2eac0aa1d3f6
[dataimport] ucsvreader should skip empty lines unless specified otherwise. Closes #3035944
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents:
diff
changeset
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''') |
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2eac0aa1d3f6
[dataimport] ucsvreader should skip empty lines unless specified otherwise. Closes #3035944
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents:
diff
changeset
|
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self.assertEqual([[u'a', u'b', u'c', u'd', u''], |
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2eac0aa1d3f6
[dataimport] ucsvreader should skip empty lines unless specified otherwise. Closes #3035944
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents:
diff
changeset
|
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[u'1', u'2', u'3', u'4', u''], |
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2eac0aa1d3f6
[dataimport] ucsvreader should skip empty lines unless specified otherwise. Closes #3035944
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents:
diff
changeset
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], |
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2eac0aa1d3f6
[dataimport] ucsvreader should skip empty lines unless specified otherwise. Closes #3035944
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents:
diff
changeset
|
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list(dataimport.ucsvreader(stream))) |
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2eac0aa1d3f6
[dataimport] ucsvreader should skip empty lines unless specified otherwise. Closes #3035944
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents:
diff
changeset
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stream.seek(0) |
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2eac0aa1d3f6
[dataimport] ucsvreader should skip empty lines unless specified otherwise. Closes #3035944
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents:
diff
changeset
|
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self.assertEqual([[u'a', u'b', u'c', u'd', u''], |
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2eac0aa1d3f6
[dataimport] ucsvreader should skip empty lines unless specified otherwise. Closes #3035944
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents:
diff
changeset
|
20 |
[u'1', u'2', u'3', u'4', u''], |
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2eac0aa1d3f6
[dataimport] ucsvreader should skip empty lines unless specified otherwise. Closes #3035944
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents:
diff
changeset
|
21 |
[u'', u'', u'', u'', u''], |
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2eac0aa1d3f6
[dataimport] ucsvreader should skip empty lines unless specified otherwise. Closes #3035944
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents:
diff
changeset
|
22 |
[u'', u'', u'', u'', u''] |
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2eac0aa1d3f6
[dataimport] ucsvreader should skip empty lines unless specified otherwise. Closes #3035944
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents:
diff
changeset
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23 |
], |
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2eac0aa1d3f6
[dataimport] ucsvreader should skip empty lines unless specified otherwise. Closes #3035944
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents:
diff
changeset
|
24 |
list(dataimport.ucsvreader(stream, skip_empty=False))) |
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2eac0aa1d3f6
[dataimport] ucsvreader should skip empty lines unless specified otherwise. Closes #3035944
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents:
diff
changeset
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9695
aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
|
26 |
def test_skip_first(self): |
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
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stream = StringIO('a,b,c,d,\n' |
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
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'1,2,3,4,\n') |
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
|
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reader = dataimport.ucsvreader(stream, skipfirst=True, |
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
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ignore_errors=True) |
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
|
31 |
self.assertEqual(list(reader), |
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
|
32 |
[[u'1', u'2', u'3', u'4', u'']]) |
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
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33 |
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
|
34 |
stream.seek(0) |
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
|
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reader = dataimport.ucsvreader(stream, skipfirst=True, |
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
|
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ignore_errors=False) |
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
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37 |
self.assertEqual(list(reader), |
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
|
38 |
[[u'1', u'2', u'3', u'4', u'']]) |
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
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39 |
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
|
40 |
stream.seek(0) |
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
|
41 |
reader = dataimport.ucsvreader(stream, skipfirst=False, |
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
|
42 |
ignore_errors=True) |
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
|
43 |
self.assertEqual(list(reader), |
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
|
44 |
[[u'a', u'b', u'c', u'd', u''], |
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
|
45 |
[u'1', u'2', u'3', u'4', u'']]) |
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
|
46 |
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
|
47 |
stream.seek(0) |
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
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48 |
reader = dataimport.ucsvreader(stream, skipfirst=False, |
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
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ignore_errors=False) |
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
|
50 |
self.assertEqual(list(reader), |
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
|
51 |
[[u'a', u'b', u'c', u'd', u''], |
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
|
52 |
[u'1', u'2', u'3', u'4', u'']]) |
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aa982b7c3f2a
[dataimport] Prevent ucsvreader from skipping the first line when ignore_errors is True (closes #3705791)
Rémi Cardona <remi.cardona@logilab.fr>
parents:
9181
diff
changeset
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53 |
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9181
2eac0aa1d3f6
[dataimport] ucsvreader should skip empty lines unless specified otherwise. Closes #3035944
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents:
diff
changeset
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54 |
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2eac0aa1d3f6
[dataimport] ucsvreader should skip empty lines unless specified otherwise. Closes #3035944
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents:
diff
changeset
|
55 |
if __name__ == '__main__': |
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2eac0aa1d3f6
[dataimport] ucsvreader should skip empty lines unless specified otherwise. Closes #3035944
Sylvain Thénault <sylvain.thenault@logilab.fr>
parents:
diff
changeset
|
56 |
unittest_main() |